The present invention relates to a low-voltage differential signaling (LVDS) output driver. More particularly, this invention relates to an LVDS output driver with a tri-statable output, programmable output current, programmable output resistance, and programmable pre-emphasis circuitry.
Low-voltage differential signaling (LVDS) is one of many I/O standards used in high-speed data transmission. A basic LVDS system includes an output driver and a receiver, connected by a pair of leads (e.g., copper traces, transmission lines, etc.) each having a fixed impedance (e.g., 50Ω). The output driver converts a differential logic signal into a low-level current, which, depending on the polarity of the signal, flows from one of two outputs towards the receiver. The current passes through a termination resistor at the receiver and flows back to the output driver. The receiver detects the direction of the current flow through the termination resistor to determine the polarity of the input differential signal and generates a corresponding full-scale logic signal.
LVDS offers several technological advantages over other standards, such as, for example, positive emitter controlled logic (PECL) and transistor—transistor logic (TTL). One advantage of LVDS is that an LVDS output driver may transmit signals at high speeds (e.g., over 1 Gbps) because the output current of the output driver does not spike at transitions of the input (e.g., from a high bit to a low bit, etc.).
Another advantage of LVDS is that the LVDS output driver generates a low current, which results in low power consumption by the output driver. This allows portable electronic devices (e.g., laptop computers) that use LVDS to consume less battery power. These and other advantages make LVDS an attractive choice for designers of high-speed systems.
However, despite the advantages of LVDS over other standards, current LVDS output drivers lack the flexibility to be programmed for or adapted to specific applications. For example, LVDS output drivers may only be coupled to receivers in a one-to-one configuration because their outputs are not tri-statable. Not only may a tri-statable output driver deactivate its output independent from the input, several tri-statable output drivers may be coupled to one or more receivers because when deactivated, a tri-statable output driver has an infinite output resistance. A tri-statable output driver may also include hot-socketing capabilities, which allows the output driver to be inserted or removed from a multi-driver system without interfering with signal transmission of another output driver.
Furthermore, the current sources of the LVDS output driver are not programmable. The output current of LVDS output drivers is typically fixed at 3 mA. However, certain LVDS applications prefer a lower or higher current. For example, the source current may be reduced to lower the power consumption of the output driver. Conversely, the source current may be increased to compensate for current diverted by additional circuitry in the output driver.
Furthermore, the output impedance of the LVDS output driver is not programmable. The characteristic output impedance of the LVDS output driver is high because of the theoretically infinite impedance of the current sources. If the output driver is coupled to the receiver as is, reflections and transmission loss will occur at high frequencies (because of the impedance mismatch between the output driver and the board traces). One known approach to matching the impedance of the output driver with that of the board trace is to use additional compensation circuitry (e.g., a parallel resistor at the output of the LVDS output driver). However, this approach may reduce the voltage drop across the termination resistor (i.e., by diverting current away from the termination resistor) while consuming the same amount of power.
Furthermore, LVDS signals typically have low edge rates and LVDS output drivers do not contain circuitry for adjusting the edge rates of the LVDS signals. Low edge rates may prevent the receiver from identifying bit transitions at high data transfer rates. For example, a bit transition from a low bit to a high bit may be incorrectly identified if the signal has not risen past the threshold for the receiver to identify the bit as a high bit.